1. Field of the Invention
The invention relates to a configuration for voltage buffering in dynamic memories using CMOS technology.
In DRAMs (dynamic random access memories), capacitive voltage buffering is required as a storage reservoir in particular for an amplified or boosted word line voltage (xe2x80x9cword line boosterxe2x80x9d) VPP, an internal regulated supply voltage VDD and a negative word line reverse voltage NWLL. This voltage buffering should save as much space as possible in order to save chip area. Despite considerable efforts, this aim has not been achieved heretofore. Thus, the various voltages required in DRAMs are currently buffered for the purpose of stabilization with the aid of MOS capacitances, for which the gate oxide is preferably used, and/or memory cells in the trench or stack. As a general rule additional, separate chip area is used for this purpose, which is contrary to the goal of a space-spacing voltage buffering.
It is accordingly an object of the invention to provide a configuration for voltage buffering in dynamic memories using CMOS technology which overcomes the above-mentioned disadvantages of the heretofore-known configurations of this general type and which provides sufficient buffer capacitances without requiring additional space on the chip.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration for voltage buffering in a dynamic memory using CMOS technology, including:
a p-conducting semiconductor substrate to be connected to a low supply voltage for supplying a first voltage thereto;
an n-conducting well structure provided in the p-conducting semiconductor substrate, the n-conducting well structure to be connected to a high supply voltage for supplying a second voltage thereto and being supplied with a given voltage to be buffered;
a p-conducting semiconductor region enclosed by the n-conducting well structure, the the p-conducting semiconductor region being supplied with a third voltage, the second voltage being higher than the first voltage and the third voltage; and
an NMOS transistor provided in the p-conducting semiconductor region.
In accordance with another feature of the invention, the n-conducting well structure is supplied with a negative word line reverse voltage as the given voltage to be buffered.
In accordance with yet another feature of the invention, the n-conducting well structure is supplied with an amplified word line voltage as the given voltage to be buffered.
In accordance with a further feature of the invention, a further well structure and a further transistor enclosed by the further well structure are provided, the n-conducting well structure and the further well structure being connected in parallel.
The invention can also be realized using the respectively inverted conduction types, such that the configuration for voltage buffering includes:
an n-conducting semiconductor substrate to be connected to a high supply voltage for supplying a first voltage thereto;
a p-conducting well structure provided in the n-conducting semiconductor substrate, the p-conducting well structure to be connected to a low supply voltage for supplying a second voltage thereto and being supplied with a given voltage to be buffered;
an n-conducting semiconductor region enclosed by the p-conducting well structure, the n-conducting semiconductor region being supplied with a third voltage, the second voltage being lower than the first voltage and the third voltage; and
a PMOS transistor provided in the n-conducting semiconductor region.
In other words, the object of the invention is achieved by the n-conducting well structure having a higher voltage applied to it than the p-conducting semiconductor region or the p-conducting semiconductor substrate and, to that end, the semiconductor substrate is connected to a low supply voltage VSS and the n-conducting well structure is connected to a high supply voltage, with the result that a voltage to be buffered can be applied to the n-conducting well structure. The voltage to be buffered is preferably the negative word line reverse voltage or the amplified or boosted word line voltage. Through the use of suitable circuit connections of the well structure, of the semiconductor substrate surrounding the well structure, and of the semiconductor region surrounded by the well structure, it is thus possible to use the large-area junction capacitances, provided by the well structure and the semiconductor substrate or by the well structure and the semiconductor region, underneath the NPN transistor in an extremely space-saving manner, in order to produce the necessary buffer capacitances. The only prerequisite for this is that a higher voltage is applied to the n-conducting well structure than to the p-conducting semiconductor region or to the p-conducting semiconductor substrate.
As described above, the invention can also be realized using the respectively inverted conduction types. In this case, a lower voltage must then be applied to the p-conducting well structure than to the n-conducting semiconductor region or the n-conducting semiconductor substrate.
The invention thus makes it possible to buffer different voltages with respect to one another without taking up additional chip area.
The main areas of application of the configuration according to the invention can be summarized as follows:
(a) In DRAMs driven by NMOS selection transistors, a large capacitive voltage reservoir of a boosted or increased word line voltage (VPP) in excess of the operating voltage is generally required in order to be able to rapidly ensure a required activation of the word line. For this purpose, use is currently made of MOS transistors or separate cell array structures with corresponding storage capacitances, but these require additional chip area and, moreover, their efficacy and reliability is limited by possible short circuits. The invention provides an outstanding remedy here: the capacitance which is present as a result of the well structure and which constitutes a junction diode capacitance for which an oxide breakdown is not possible is used without additionally taking up chip area underneath the NMOS field-effect transistors that are present in any case. Short circuits are not to be expected and consequently the reliability is high. Moreover, as has already been mentioned, no additional chip area is required.
(b) The invention may be used especially in the case of the xe2x80x9cnegative word line lowxe2x80x9d technique (technique in which a negative word line is at low voltage) that will probably be used in the future, and in which word lines in the switched-off state are not pulled to ground VSS but rather are at a negative voltage value. Here, in order to improve the off state of the NMOS selection transistors, it is possible, due to the insulated NMOS field-effect transistors which are required in the row decoder, to use the well structure of the transistors for the required support of the ground buffering.
As will be explained in more detail further below with reference to an exemplary embodiment, standard NMOS field-effect transistors can be provided in insulated semiconductor regions, even in existing configurations. Their buried well structures then serve as buffers wherein an extremely small space is taken up for the implantation of a connection region (xe2x80x9cWN implantationxe2x80x9d) all around the n-conducting well structure.
(c) Quite generally it is also possible to provide the on-chip supply voltage VDD or any other generator voltage under insulated NMOS field-effect transistors, in order to increase the stabilization.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration for voltage buffering in dynamic memories using CMOS technology, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.